1. Field of the Invention
The present invention relates to semiconductor devices and methods of fabricating the same and, more particularly, to cylindrical capacitors having a stepped sidewall and methods for fabricating the same.
2. Description of the Related Art
With continuing efforts to increase integration density, semiconductor integrated circuit devices become smaller and are spaced to each other more closely than ever. Accordingly, cell capacitors of a highly integrated dynamic random access memory (DRAM) become smaller and smaller. When the cell capacitance is reduced, memory cells can suffer from soft error due to alpha particles and can easily lose their stored data. Thus, the cell capacitance of the highly integrated DRAM should be increased to improve cell characteristics such as soft error.
Along this line, three-dimensional cell capacitors, e.g., cylindrical capacitors are widely employed in the highly integrated DRAM to increase the cell capacitance.
FIG. 1 is a cross sectional view showing conventional cylindrical capacitors.
Referring to FIG. 1, an interlayer insulating layer 110 is formed on a semiconductor substrate (not shown). The interlayer insulating layer 110 is patterned to form a plurality of storage node contact holes in the interlayer insulating layer 110. Each of the storage node contact holes is filled with a storage node contact plug 112. An etch stopping layer 114 and a molding layer (not shown) are sequentially formed on an entire surface of the substrate having the storage node contact plugs 112. The molding layer and the etch stopping layer 114 are successively etched to form a plurality of storage node holes that expose the respective storage node contact plugs 112. In this case, the storage node holes have sloped sidewalls. In particular, the thicker the molding layer is, the more sluggish the slope of the sidewall is. Cylindrical storage nodes 116 are then formed in the storage node contact holes. Thus, the sidewalls of the storage nodes 116 are also inclined along the sidewalls of the storage node contact holes as shown in FIG. 1. As a result, it is difficult to increase surface areas of the cylindrical storage nodes 116 at the base thereof.
The present invention provides methods for fabricating a cylindrical capacitor with a storage node having a stepped sidewall to increase capacitance.
Another feature of the present invention is to provide cylindrical capacitors including a storage node that has an increased surface area.
According to an aspect of the present invention, the cylindrical capacitor includes a semiconductor substrate and a cylindrical storage node stacked on the semiconductor substrate. The storage node has a base and a stepped sidewall on the base. The stepped sidewall has at least two sub-sidewalls, which are sequentially stacked, and at least one joint portion that connects a lower sidewall of the two sub-sidewalls to an upper sidewall on the lower sidewall. Here, an upper diameter of the respective sub-sidewalls is greater than a lower diameter thereof. Also, an upper diameter of the lower sidewall is greater than a lower diameter of the upper sidewall. Accordingly, a step is formed between the two sub-sidewalls, which are adjacent to each other.
In addition, an interlayer insulating layer may be interposed between the cylindrical storage node and the semiconductor substrate. The cylindrical storage node is electrically connected to the semiconductor substrate via a storage node contact plug formed within a storage node contact hole that penetrates a portion of the interlayer insulating layer.
According to another aspect of the invention, the invention is directed to a method for fabricating a cylindrical capacitor. The method includes providing a semiconductor substrate. A plurality of molding layers are sequentially formed over the semiconductor substrate. An etch rate of a lower molding layer of the plurality of molding layers is faster than that of an upper molding layer on the lower molding layer with respect to a predetermined etchant such as an oxide etchant. The plurality of molding layers are patterned to form a preliminary storage node hole that exposes a portion of the semiconductor substrate. The molding layers are isotropically etched using the etchant to form a storage node hole. Accordingly, the storage node hole has a stepped sidewall profile. A cylindrical storage node is then formed in the storage node hole. A sidewall of the storage node is conformably formed along the stepped sidewall profile of the storage node hole. Hence, the cylindrical storage node has a stepped sidewall.
Preferably, a thickness of the lower molding layer is less than that of the upper molding layer on the lower molding layer.
In addition, the molding layers are preferably a borophosphosilicate glass (BPSG) layer and an undoped silicate glass (USG).
Further, an interlayer insulating layer may be formed on the semiconductor substrate prior to formation of the plurality of molding layers. In this case, the interlayer insulating layer is patterned to form a storage node contact hole that exposes a portion of the semiconductor substrate, and a storage node contact plug is formed within the storage node contact hole. Also, the storage node hole is formed to expose the storage node contact plug. Accordingly, the storage node is electrically connected to the semiconductor substrate via the storage node contact plug.